Power nets management

A recent BugCrunch item (Power input vs output) raised the long standing issue of power management in Altium Designer. To ensure we are all on the same page, I have some opinions I think are worth sharing before work gets started. As always, I will be very interested in your thoughts and comments. My aim is to make sure that what we do with regards to this is ultimately useful in real life.

First, let me describe the problem as I see it and how I think it should be addressed.

In Altium Designer today, power pins are generally used to indicate a user of power. Power pins can be treated differently from other pins at ERC time.

However, it is not possible to easily identify and manage complete power distribution systems.

Consequently, a greater level of care is required to avoid fatal errors like power starved components or shorts (which I am sure keep many up at night).

At the board design level, the set of nets that distribute power constitutes a ‘power network’. Similarly, the set of nets that collect current to ground constitutes another ‘power network’.

Within each of these power networks, a unique point connects to external power resources (either a power source that provides power, or a connection to ground). The net that is connected to this point is truly a power net.

Also within each of these power networks, a number of parts (current limiting resistors, net-ties, fuses, etc.) are ‘see-through’ components that, from the point of view of the whole network, are only a connection (though a connection that bears certain required characteristics) joining one net to another .

The following is an abstract representation of such power-network at the board level.

In the drawing above, the nets drawn in red, and the nets within the red box constitute a whole power network. Within this network, a power net directive identifies the net ‘Main PWR’ as the unique net through which power is actually delivered.

The nets drawn in blue, and the nets  within the blue box would constitute another whole power network. Within this network, a power net directive identifies the net ‘Main GND’ as the unique net that is actually connected to the ground.

In each power network, only one net can be identified as a power net. Also, each net containing power related objects should be part of a power network.

In the schematics of PCB projects, a new directive will be available, called ‘Power net directive’. When placed on a given net, it will identify it as the unique net (within a power network) that connects to external power resources.

This new directive can look like this to be easily identified.

Also, a new schematic object will be introduced, called “Part See-Through”.

It will be placed by choosing two pins (from the same part) hotspots, and it will link them.

Its graphical representation will be something similar to this (this was drawn using the line and elliptical arc objects)

Part see-through’s color, thickness, line style (full or dotted line) and style (arc or line) will be controllable and determine their graphical aspect. Upon placement, part see-thoughs will be automatically ‘unionized’ with the part they target, so they can be easily moved together.

In effect, the role of a part see-through is to join two nets in a ‘group of two nets’. Consequently, a group of part see-throughs, used in combination with a power net directive will  define a whole power network.

Note that net ties components will be entirely see through by default

All standard editing and management system ( Dialog, Inspector, List, Queries, parametrization for scripts) should support these new objects and fields.

Based on these elements, some intelligence about a design power network can be gathered by the system, and reported in a useful way.

New compilation errors can indicate incoherent situations which could lead to errors in the manufactured board

1. Missing power net directive on power network.
2. Power net directive conflict on power network.
3. Missing power pin on power net.
4. Starved local power net.

Also, power to input pin errors and input pins without a driver errors can be more intelligently handled in the case of pull-ups or pull-downs: if the nets involved are part of a properly declared power network, these errors can be suppressed.

Also net classes can be generated based on declared power networks.

Finally power networks can be precisely described in reports formatted for this purpose.

A power networks report will contain information about:

1. The list of nets involved in a given power network
2. The list of components and their see-through pin pairs involved in the power network
3. The details of the power net of a given power network.
4. The list of the whole network ‘boundary pins’.

In the future, this intelligence can also be put to good use first to improve the schematic representation (through automatic wire coloring based on power networks), but also most importantly at the PCB level, to easily identify and manage power networks. Part see-throughs could also be used for other purposes, like managing the length of signal nets that contain dampening resistors